R8 is an experimental 8bit cisc processor which is written using verilog. The verilog design uses behaviour modeling.
Hardware was synthesized on Altera FPGA (WXEDA v2 Board and WaveShare Core EP4CE6 Board).
(Following files are released under the MIT license.)
Download CPU Source
Full System For WXEDA v2 Board (Quartus Prime Project Files)
reading: mov1 ax, addr writing: mov2 addr, ax mov3 addr, value flow control: jmp1 addr je addr jne addr jl addr jle addr jg addr jge addr arithmetic: inc ax cmp ax, value
mov3 04h 00h, 01h ; write 1 into R8LED (device4) mov3 03h 00h, 00h ; write to R8Delay (device3) mov3 04h 00h, 00h ; write 0 into R8LED mov3 03h 00h, 00h ; write to R8Delay jmp1 01h 00h ; jump to start
03 04 00 01 03 03 00 00 03 04 00 00 03 03 00 00 04 01 00
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